# verilog hdl中怎么判断闰年，下面的程序判断不出来是怎么回事？

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[待解决问题]

module nyr2014(clk,qy,qn,qr);
input clk;
output[7:0] qy,qr;
output [15:0] qn;
reg[7:0] qy,qr;
reg[15:0] qn;
reg clkn,clky;
reg[7:0] date;
reg clkn1;
initial
begin clkn1=1;
end
initial

begin qn='h1900;end
always@(posedge clk)

begin
if(qr==date)
begin qr=1;clky=1;end
else if(qr[7:4]==date[7:4]&&qr[3:0]==date[3:0])
begin qr[7:4]<=qr[7:4];qr[3:0]<=qr[3:0];clky<=1;end
else if(qr[3:0]==9)
begin qr[7:4]<=qr[7:4]+1;qr[3:0]=0;end
else if(qr[7:4]<date[7:4]&&qr[3:0]<date[3:0])
begin qr[7:4]<=qr[7:4];qr[3:0]<=qr[3:0]+1;clky<=0;end
else begin qr[7:4]=qr[7:4];qr[3:0]=qr[3:0]+1;clky<=0;end
end

always @ (posedge clky )
begin
if(qy=='h12)
begin qy=1;clkn=1; end
else if(qy<'h12)
begin qy=qy+1;clkn<=0; end
if(qy[3:0]=='ha)
begin qy[3:0]=0; qy[7:4]=qy[7:4]+1;clkn<=0;end
end
always
begin case(qy)
'h01:date='h31;
'h02: begin if((qn%4===0)&&( qn%100!==0)||( qn%400===0))
//if(((qn%4===0)&(qn%100!==0))|(qn%400===0))
date='h29;
else date='h28; end
'h03:date='h31;
'h04:date='h30;
'h05:date='h31;
'h06:date='h30;
'h07:date='h31;
'h08:date='h31;
'h09:date='h30;
'h10:date='h31;
'h11:date='h30;
'h12:date='h31;
default:date='h30;
endcase
end
endmodule

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gltide | 园豆：403 (菜鸟二级) | 2014-11-13 10:07

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